Processing apparatus and method of the same

ABSTRACT

A processing apparatus capable of reducing the size of the circuit, where in order to perform an operation “(A−B)×C”, provision is made of multiplexers  50   0  to  50   15  provided corresponding to each of all combinations of natural numbers i and j which receive as their inputs bit data A i , B i , and C j , output the bit data A i  when the C j  has the logical value “1”, and output the bit data B i when the C j  has the logical value “0”, and the bit data output from the multiplexers  50   0  to  50   15 , data obtained by shifting the complement data of 2 of the data B by exactly n bits toward the most significant bit, the data B and the carry data as the carrying from the lower significant bit are added for every bit so as to add the bit data output from the multiplexers  50   0  to  50   15  to the (i+j)th bit.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a processing apparatus and a method of the same. 2. Description of the Related Art

A processing apparatus which receives as its inputs positive binary data A, B, and C and performs an operation “(A−B)×C”, is known in the art.

Below, an explanation will be made of a processing apparatus of the related for performing the operation “(A−B)×C”.

FIG. 6 is a view of the configuration of the processing apparatus of the related for performing the operation “(A−B)×C”.

As shown in FIG. 6, the processing apparatus 1 has a subtracter 2 and a multiplier 3 and performs the operations “(A−B)×C” by using the 4-bit data A, B, and C.

The processing apparatus 1, for example, performs the subtraction of the 4-bit data A and the 4-bit data B at the subtracter 2 and the multiplication of the signed 5-bit subtraction result Y and the 5-bit data C with a most significant bit (MSB) having a logical value “0” due to code expansion at the multiplier 3. Then, the multiplication result of the multiplier 3 becomes the result of the operation “(A−B)×C”.

As the subtracter 2, for example, as shown In FIG. 7. a ripple carry type adder comprised of full adders (FA) 10 ₀, 10 ₁, 10 ₂, and 10 ₃ connected in series, is used.

In this subtracter 2, “1” for finding a complement of 2 is Input to a Ci (Carry In) terminal of the full adder 10 ₁ performing the operation corresponding to the least significant bit (LSB). Further, the bit data A₀ to A₃ of the data A are Input to the full adders 10 ₀ to 10 ₃ and the bit data B₀ to B₃ of the data B are Input via inverters 11 ₀ to 11 ₃. Then, bit data Y₀ to Y₃ of the 4-bit result Y are output from s terminals of the full adders 10 ₀ to 10 ₃ and bit data Y₄ indicating the sign of the subtraction result Y Is output from a CO (Carry Out) terminal of the full adder 10 ₃.

Note that, as the full adders 10 ₁ to 10 ₃, as shown In FIG. 8, use is made of a general full adder constituted by combining AND circuits 15 ₁, and 15 ₂, OR and 17 ₂. At the full adders 10 ₁ to 10 ₃, bit data input through an in₁ terminal, in₂ terminal, and Ci (Carry in ) terminal are added, the carry of the addition result Is output from the CO (Carry out) terminal, and sum data Is output from the S terminal.

Next, an explanation will be made of the configuration of the multiplier 3 shown In FIG. 6.

FIG. 9 Is a view for explaining a complement multiplication of 2 according to the Baugh Wooly method adopted by the multiplier 3.

A FIG. 10 is a view of the configuration of the multiplier 3 performing the complement multiplication of 2 shown in FIG. 9.

As shown in FIG. 10, the multiplier 3 has a partial product adder circuit 20 and a final stage adder circuit 30.

The partial product adder circuit 20 adopts the Wallace-tree method and has AND circuits 21 ₀ to 21 ₂₄, full adders 22 ₁ to 22 ₁₃, half adders 23 ₁ to 23 ₃, and inverter circuits 24 ₁ to 24 ₁₁.

Further, the final adder circuit 30 adopts the Ripple Carry method and has full adders 22 ₁₄ to 22 ₁₉ and half adders 23 ₄ and 23 ₅.

Here, the full adders 22 ₁₄ to 22 ₁₉ have the configuration shown in FIG. 8 mentioned above. Further, as the half adders 23 ₁ to 23 ₃, as shown in FIG. 11, provision is made of an AND circuit 15 ₃ and an XOR circuit 17 ₃, data input through the in terminal and the in₂ terminal are added, the carry of the related addition result is output from the CO (Carry Out) terminal, and the sum data is output from the S terminal.

At the multiplier 3, the AND circuits 21 ₁ to 21 ₂₄ of the partial product adder circuit 20 use the bit data Y₀, Y₁, Y₂, Y₃, and Y₄ of the subtraction result Y from the subtracter 2 and the bit data C₀, C₁, C₂, C₃, and 0 with an MSB having the logical value “0” due to code expansion for the partial products shown in FIG. 9. Then, the partial products are added at the full adders 22 ₁ to 22 ₁₉ and the half adders 23 ₁ to 23 ₅ of the partial product adder circuit 20 and the final stage adder circuit 30 including a carry from a lower digit for every digit. By this, sum data output from the output terminal of the AND circuit 21 ₀ and s terminals of the half adders 23 ₁ and 23 ₄, the full adders 22 ₁₄, 22 ₁₅, 22 ₁₆, 22 ₁₇, 22 ₁₈, and 22 ₁₉, and the half adder 23 ₅ become bit data S₀, S₁, S₂, S₃, S₄, S₅, S₆, S₇, S₈, and S₉ of the 10-bit result S.

Summarizing the problem to be solved by the invention, in the processing apparatus 1 of the related art mentioned above, as shown in FIG. 7 and FIG. 10, there is a disadvantage that there are the full adders 10 ₀ to 10 ₃, AND circuits 21 ₀ to 21 ₂₄, full adders 22 ₁ to 22 ₁₉, half adders 23 ₁ to 22 ₅, and inverter circuits 24 ₁ to 24 ₁₁ and the size of the circuit becomes large.

Namely, in the processing apparatus 1, as shown in FIG. 1, in order to perform the subtraction at the subtracter 2, when using 4-bit data A and B, the result thereof becomes 5 bits, including the sign bit. As a result, at the multiplier 3, it is necessary to perform the multiplication of 5 bits and the size of the circuit becomes large.

Further, in the processing apparatus 1 of the related art mentioned above, the critical path of the operation becomes the full adders 10 ₀ to 10 ₃, half adder 23 ₄, full adders 22 ₁₄, 22 ₁₅, 22 ₁₆, 22 ₁₇, 22 ₁₈, and 22 ₁₉, and the half adder 23 ₅, so there is a disadvantage that the processing time becomes long.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a processing apparatus capable of reducing the size of the circuit performing the operation “(A−B)×C”.

Another object of the present invention is to provide a processing apparatus capable of shortening the processing time of the operation “(A−B)×C”.

According to a first aspect of the present invention, there is provided a processing apparatus for calculating “(A−B)×C” where the bit data A is constituted by the n-bit data of A_(i) (i=0, 1, . . . n−1), the bit data B is constituted by the n-bit data of B_(i) (i=0, 1, . . . n−1), and the bit data C is constituted by the n-bit data of C_(j) (j=0, 1, . . . n−1), said processing apparatus comprising: a bit data selecting means for receiving as input the bit data A_(i), B_(i), and C_(j), and outputting the bit data A_(i) when C_(j) equals to a first logical value or the bit data B_(i) when data C_(j) equals to a second logical value in response to data C_(j) with respect to all combinations of the natural numbers i and J and an adding means for adding the bit data output from the bit data selecting means to the (i+j)th bit for each bit of all combinations of i and j, the data obtained by shifting the data of the complement of 2 of the data B by exactly n number of bits toward the most significant bit, and the data B.

The processing apparatus of the present invention performs the operation “(A−B)×C” based on the following equation (1): $\begin{matrix} {S = {\left( {\sum\limits_{j = 0}^{j = {n - 1}}{\sum\limits_{i = 0}^{i = {n - 1}}{\cdot \left( {A_{j} \cdot C_{j}} \middle| {B_{i} \cdot {\overset{\_}{C}}_{j}} \right)}}} \right) - {2^{n} \times B} + B}} & (1) \end{matrix}$

That is, in the processing apparatus of the present invention, each of the plurality of bit data selecting means outputs the bit data A_(i) when the input C_(j) is the logical value “1” and outputs the bit data B_(i) when C_(j) is the logical value “0” among the input bit data A_(i) and B_(i).

Next, the adding means adds the bit data output from the bit data selecting means to the (i+j)th bit by adding for each bit the bit data output from the bit data selecting means, the data obtained by shifting the data of the complement of 2 of the data B by exactly n number of bits toward the most significant bit, the data B, and the carry data carried from a lower bit.

Preferably, it further provides with an inverted value generating means for inverting the bit data B₀, B₁, . . . , B_(i), . . . , B_(n−2), and B_(n−1) to find the bit data B₀ ⁻, B₁ ⁻, . . . , B_(i) ⁻, . . . , B_(n−2) ⁻, and B_(n−1) ⁻; the adding means respectively adds the bit data B₁ ⁻, . . . , B_(i) ⁻, . . . , B_(n−1) ⁻, found by the inverted value generating means to the (n+1)th, . . . , (n+i)th, . . . , (2n−1)th bits and adds the bit data B₀ ⁻ and the logical value “1” to the n-th bit.

Preferably, the adding means adds the bit data B₀, B₁, . . . , B_(i), . . . , B_(n−2), and B_(n−1) of the data B to the 0th, 1st, . . . , i-th, . . . , (n−2)th, and (n−1)th bits.

Preferably, the adding means outputs as the result of the addition (2n+1)bit data comprised of the bit data S₀, S₁, . . . , S_(2n−1) and S_(2n) and the bit data S_(2n) shows the sign value.

Preferably, the bit data selecting means each has a first transmission gate which becomes conductive when the input bit data C_(i) is the logical value “1” and a second transmission gate which becomes conductive when the input bit data C_(i) is the logical value “0”.

According to a second aspect of the present invention, there is provided a processing method for calculating “(A−B)×C” where the bit data A is constituted by the n-bit data of A_(i) (i=0, 1, . . . n−1), the bit data B is constituted by the n-bit data of B_(i) (i=0, 1, . . . n−1), and the bit data C is constituted by the n-bit data of C_(j) (j=0, 1, . . . n−1), said processing method comprising the steps of: performing processing for receiving as input the bit data A_(i), B_(i), and C_(j), selecting the bit data A_(i) when data C_(j) equals to a first logical value or B_(i) when data C_(j) equals to a second logical value in response to the bit data C_(j) with respect to all combinations of the natural numbers i and j and adding the selected bit data to the (i+j)th bit for each bit of all combination of i and j, the data obtained by shifting the data of the complement of 2 of the data B by exactly n number of bits toward the most significant bit, and the data B.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects and features of the present invention will become more apparent from the following description of the preferred embodiments given with reference to the attached drawings, wherein:

FIG. 1 is a view of the configuration of a processing apparatus according to the present embodiment;

FIG. 2 is a view of the configuration of a multiplexer shown in FIG. 1;

FIG. 3 is a view for explaining a processing method adopted by the processing apparatus shown in FIG. 1;

FIG. 4 is a flow chart for explaining the operation of the processing apparatus shown in FIG. 1;

FIG. 5 is a view for explaining a concrete operation in the processing apparatus shown in FIG. 1;

FIG. 6 is a view of the configuration of the processing apparatus of the related art performing an operation “(A−B)×C”;

FIG. 7 is a view of the configuration of a subtracter shown in FIG. 6;

FIG. 8 is a view of the configuration of a full adder (FA) shown in FIG. 7;

FIG. 9 is a view for explaining a complement multiplication of 2 by the Baugh Wooly method adopted by the multiplier shown in FIG. 2;

FIG. 10 is a view of the configuration of the multiplier for performing the complement multiplication of 2 shown in FIG. 9; and

FIG. 11 is a view of the configuration of the half adder shown in FIG. 10.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Below, an explanation will be made of a processing apparatus according to an embodiment of the present invention and a method of the same.

FIG. 1 is a view of the configuration of a processing apparatus 40 for performing an operation “S=(A−B)×C” using the 4-bit data A, B, and C.

As shown in FIG. 1, the processing apparatus 40 has a partial product adder circuit 41 and a final stage adder circuit 42.

The partial product adder circuit 41 has multiplexers 50 ₀ to 50 ₁₅ as the bit data selecting means of the present invention, full adders (FA) 52 ₁ to 52 ₁₀, half adders (HA) 53 ₁ to 53 ₃, inverter circuits 54 ₁ to 54 ₄, input units 55 and 56, and an output unit 57.

The final stage adder circuit 42 has full adders 52 ₁₁, to 52 ₁₆ and a half adder 53 ₄.

The input unit 55 has A₀, A₁, A₂, A₃, B₀, B₁, B₂, and B₃ terminals for receiving as their inputs bit data A₀, A₁, A₂, A₃, B₀, B₁, B₂, and B₃.

Here, the 4-bit data A is comprised by bit data A₀, A₁, A₂, and A₃, while the 4-bit data B is comprised by bit data B₀, B₁, B₂, and B₃.

The input unit 56 has C₀, C₁, C₂, and C₃ terminals for receiving as input bit data C₀, C₁, C₂, and C₃.

Here, the 4-bit data C is comprised by the bit data C₀, C₁, C₂, and C₃.

The output unit 57 has S₀, S₁, S₂, S₃, S₄, S₅, S₆, S₇, and S₈ terminals for outputting bit data S₀, S₁, S₂, S₃, S₄, S₅, S₆, S₇, and S₈.

Here, the 9-bit data S is comprised by the bit data S₀, S₁, S₂, S₃, S₄, S₅, S₆, S₇, and S₈.

The multiplexers 50 ₀ to 50 ₁₅ find partial products P_(0,0), P_(1,0), P_(0,1), P_(2,0), P_(1,1), P_(0,2), P_(3,0), P_(2,1), P_(1,2), P_(0,3), P_(3,1), P_(2,2), P_(1,3), P_(3,2), P_(2,3), and P_(3,3) defined by the following equation (2):

P_(ij)=A_(i)·Cj|B_(i)·{overscore (C)}_(j)(i=0˜3j=0˜3)  (2)

FIG. 2 is a view of the configuration of multiplexers 50 ₀ to 50 ₁₅.

As shown in FIG. 2, the multiplexers 50 ₀ to 50 ₁₅ have inverters 70 ₁ to 70 ₄, transmission gates 70 ₁ and 70 ₂, an s terminal, an a terminal, a b terminal, and an o terminal.

At the multiplexers 50 ₀ to 50 ₁₅, when the s terminal has a logical value “1”, the transmission gate 70 ₁ is turned off, the transmission gate 70 ₂ is turned on, and the level of the a terminal is output as the level of the o terminal. On the other hand, at the multiplexers 50 ₀ to 50 ₁₅, when the s terminal has a logical value “0”, the transmission gate 70 ₁ is turned on, the transmission gate 70 ₂ is turned off, and the level of the b terminal is output as the level of the o terminal.

Namely, at the multiplexers 50 ₀ to 50 ₁₅, a bit data A_(i) input to the a terminal is output from the o terminal when a bit data C_(j) has the logical value “1”, and a bit data B_(i) input to the a terminal is output from the o terminal when the bit data C_(j) has the logical value “0”.

Partial products P_(0,0), P_(1,0), P_(0,1), P_(2,0), P_(1,1), P_(0,2), P_(3,0), P_(2,1), P_(1,2), P_(0,3), P_(3,1), P_(2,2), P_(1,3), P_(3,2), P_(2,3), and P_(3,3) calculated at the multiplexers 50 ₀ to 50 ₁₅ are added containing carries from the lower significant bits for every bit at full adders 52 ₁ to 52 ₁₆ and the half adders 53 ₁ to 53 ₄ so that they are added to an (i+j)th bit. By this, the operation “A×C+B×C⁻j” shown in the following equation (3) is performed. $\begin{matrix} {{{A \times C} + {B \times \overset{\_}{C}}} = {\sum\limits_{j = 0}^{j - 3}{\sum\limits_{i + 0}^{i - 3}{2^{i + j} \cdot P_{ij}}}}} & (3) \end{matrix}$

Here, as the full adders 52 ₁ to 52 ₁₆, use is made of ones having the configuration shown in FIG. 8 mentioned before. Further, as the half adders 53 ₁ to 53 ₄, use is made of ones having the structure shown in FIG. 11 mentioned before.

The inverter circuits 54 ₁, 51 ₂, and 51 ₃ to 51 ₄ receive as their inputs the bit data B₀, B₁, B₂, and B₃ and output the inverted bit data B₀ ⁻, B₁ ⁻, B₂ ⁻, and B₃ ⁻.

The operations at the inverter circuits 54 ₁ to 54 ₄ correspond to inversion operations for performing the operation “−2⁴×B”. Further, by the addition carried out by inputting “1” to the Ci (Carry in) terminal of the full adder 52 ₆, the “addition of 1” for performing the operation “−2⁴×B” is carried out.

Further, bit data B₀ to B₃ are output to the in₂ terminals of the half adder 53 ₁, full adder 52 ₁, half adder 53 ₂, and the full adder 52 ₄. At the half adder 53 ₁, full adder 52 ₁, half adder 53 ₂, and the full adder 52 ₄, the operation of “+B_(j)” is carried out.

As mentioned above, by the full adders 52 ₁ to 52 ₁₆ and the half adders 53 ₁ to 53 ₄, the operation of the following equation (4) is performed by adding the result of “A×C+B×C⁻”, “−2⁴×B”, and “B”. $\begin{matrix} {S = {\left( {\sum\limits_{j = 0}^{j = 3}{\sum\limits_{i = 0}^{i = 3}{2^{i + j} \cdot P_{ij}}}} \right) - {2^{4} \times B} + B}} & (4) \end{matrix}$

Note that the operation of the above equation (3) is represented as shown in FIG. 3.

Note that, in FIG. 3, the figures in parentheses indicate the reference numerals of the constituent elements of the processing apparatus 40 shown in FIG. 1 and indicate that the operation indicated adjoining this is found by the related constituent element or the data indicated adjoining this is input to the related constituent element.

Here, the above equation (4) is equivalent to the operation “S=(A−B)×C”.

Below, the fact that above equation (4) is equivalent to the operation “S=(A−B)×C” will be proved.

The operation “S=(A−B)×C” can be modified as in the following equation (5): $\begin{matrix} \begin{matrix} {S = {\left( {A - B} \right) \times C}} \\ {= {{A \times C} - {B \times C}}} \\ {= {{A \times C} + {B \times \left( {- C} \right)}}} \end{matrix} & (5) \end{matrix}$

A complement x⁻ of 1 of a binary x is indicated by the following equation (6):

{overscore (x)}=1·x  (7)

Accordingly, when the above equation (6) is applied to “−C” of the above equation 5), the following equation (7) stands: $\begin{matrix} {{- C} = {\overset{\_}{C}{\sum\limits_{i = 0}^{i = 3}2^{i}}}} & (7) \end{matrix}$

Further, when the above equation (5) is rewritten by using the above equation (7) and further modification is made, the result becomes the following equation (8): $\begin{matrix} \begin{matrix} {S = {{A \times C} + {B \times \left( {\overset{\_}{C} - {\sum\limits_{i = 0}^{i = 3}2^{i}}} \right)}}} \\ {= {{A \times C} + {B \times \overset{\_}{C}} - {{Bx}{\sum\limits_{i = 0}^{i = 3}2^{i}}}}} \\ {= {{A \times C} + {B \times \overset{\_}{C}{x\left( {2^{4} - 1} \right)}}}} \\ {= {{A \times C} + {B \times \overset{\_}{C}{x2}^{4} \times B} + B}} \end{matrix} & (8) \end{matrix}$

Here, it is seen from above equation (8) and equation (3) that the operation “S=(A−B)×C” is equivalent to above equation (5).

Below, an explanation will be made of a connection configuration of the constituent elements of the processing apparatus 40 shown in FIG. 1.

The a terminals of the multiplexers 50 ₁, 50 ₂, 50 ₅, and 50 ₉ are connected to the A₀ terminal of the input unit 55, and the b terminals thereof are connected to the B₀ terminal of the input unit 55.

The a terminals of the multiplexers 50 ₁, 50 ₄, 50 ₈, and 50 ₁₂ are connected to the A₁ terminal of the input unit 55, and the b terminals thereof are connected to the B₁ terminal of the input unit 55.

The a terminals of the multiplexers 50 ₃, 50 ₇, 50 ₁₁, and 50 ₁₄ are connected to the A₂ terminal of the input unit 55, and the b terminals thereof are connected to the B₂ terminal of the input unit 55.

The a terminals of the multiplexers 50 ₆, 50 ₁₀, 50 ₁₃, and 50 ₁₅ are connected to the A₃ terminal of the input 1unit 55, and the b terminals thereof are connected to the B₃ terminal of the input unit 55.

The s terminals of the multiplexers 50 ₀, 50 ₁, 50 ₃, and 50 ₆ are connected to the C₀ terminal of the input unit 56.

The s terminals of the multiplexers 50 ₂, 50 ₄, 50 ₇, and 50 ₁₀ are connected to the C₁ terminal of the input unit 56.

The s terminals of the multiplexers 50 ₅, 50 ₈, 50 ₁₁, and 50 ₁₃ are connected to the C₂ terminal of the input unit 56.

The s terminals of the multiplexers 50 ₉, 50 ₁₂, 50 ₁₄, and 50 ₁₅ are connected to the C₃ terminal of the input unit 56.

The in terminal of the half adder 53 ₁ is connected to the o terminal of the multiplexer 50 ₀, and the in₂ terminal thereof is connected to the B₀ terminal of the input unit 55.

Further, the s terminal of the half adder 53 ₁ is connected to the S₀ of the output unit 57, and the CO terminal thereof is connected to the in₂ terminal of the half adder 53 ₄.

The in₁ of the full adder 52 ₁ is connected to the o terminal of the multiplexer 50 ₂, the in₂ terminal thereof is connected to the o terminal of the multiplexer 50 ₁, and the Ci terminal thereof is connected to the B₁ of the input unit 55.

Further, the s terminal of the full adder 52 ₁ is connected to the in₁ terminal of the half adder 53 ₄, and the CO terminal thereof is connected to the in₂ terminal of the full adder 52 ₁₁.

The in₁ terminal of the half adder 53 ₂ is connected to the o terminal of the multiplexer 50 ₃, and the in₂ terminal thereof is connected to the B₂ terminal of the input unit 55.

Further, the s terminal of the half adder 53 ₂ is connected to the Ci terminal of the full adder 52 ₂, and the C₀ terminal thereof is connected to the Ci terminal of the full adder 52 ₄.

The in₁ terminal of the half adder 53 ₃ is connected to the o terminal of the multiplexer 50 ₉, and the in₂ terminal thereof is connected to the o terminal of the multiplexer 50 ₈.

Further, the s terminal of the half adder 53 ₃ is connected to the in₁ terminal of the full adder 52 ₃, and the CO terminal thereof is connected to the in₂ terminal of the full adder 52 ₇.

The full adder 52 ₅ is connected at its in₁ terminal to the o terminal of the multiplexer 50 ₁₂, connected at its in₂ terminal to the o terminal of the multiplexer 50 ₁₁ and connected at its Ci terminal to the o terminal of the multiplexer 50 ₁₀.

Further, the full adder 52 ₅ is connected at its s terminal to the in₁ terminal of the full adder 52 ₆ and connected at its CO terminal to the in₂ terminal of the full adder 52 ₉.

The full adder 52 ₈ is connected at its in₁ terminal to the o terminal of the multiplexer 50 ₁₄, connected at its in₂ terminal to the o terminal of the multiplexer 50 ₁₃, and connected at its Ci terminal to the output terminal of the inverter 54 ₂.

Further, the full adder 52 ₈ is connected at its s terminal to the in₁ terminal of the full adder 52 ₉ and connected at its CO terminal to the Ci terminal of the full adder 52 ₁₀.

The full adder 52 ₂ is connected at its in₁ terminal to the o terminal of the multiplexer 50 ₅ and connected at its in₂ terminal to the multiplexer 50 ₄.

Further, the full adder 52 ₂ is connected at its s terminal to the in₁ terminal of the full adder 52 ₁₁ and connected at its CO terminal to the in₂ terminal of the full adder 52 ₁₂.

The full adder 52 ₃ is connected at its in₂ terminal to the o terminal of the multiplexer 50 ₇ and connected at its Ci terminal to the o terminal of the multiplexer 50 ₆.

Further, the full adder 53 ₃is connected at its s terminal to the in₁ terminal of the full adder 52 ₄ and connected at its CO terminal to the Ci terminal of the full adder 52 ₇.

The in₂ terminal of the full adder 52 ₆ is connected the output terminal of the inverter 54 ₁, and the logical value “1” is input to the Ci terminal thereof.

Further, the full adder 52 ₆ is connected at its s terminal to the in₁ terminal of the full adder 52 ₇ and connected at its CO terminal to the Ci terminal of the full adder 52 ₉.

The full adder 52 ₁ is connected at its in₂ terminal to the output terminal of the inverter 54 ₃.

Further, the full adder 52 ₁₀ is connected at its s terminal to the in₁ terminal of the full adder 52 ₁₅ and connected at its CO terminal to the in₂ terminal of the full adder 52 ₁₆.

The full adder 52 ₄ is connected at its in₂ terminal to the B₃ terminal of the input unit 55.

Further, the full adder 52 ₂ is connected at its s terminal to the in₁ terminal of the full adder 52 ₁₂ and connected at its CO terminal to the in₂ terminal of the full adder 52 ₁₃.

The full adder 52 ₇ is connected at its s terminal to the in₁ terminal of the full adder 52 ₁₃ and connected at its CO terminal to the in₂ terminal of the full adder 52 ₁₄. The full adder 52 ₉ is connected at its s terminal to the in₁ terminal of the full adder 52 ₁₄ and connected at its CO terminal to the in₂ terminal of the full adder 52 ₁₅.

The half adder 53 ₄ is connected at its s terminal to the S₁ terminal of the output unit 57 and connected at its CO terminal to the Ci terminal of the full adder 52 ₁₁.

The full adder 52 ₁₁ is connected at its s terminal to the S₂ terminal of the output unit 57 and connected at its CO terminal to the Ci terminal of the full adder 52 ₁₂.

The full adder 52 ₁₂ is connected at its s terminal to the S₃ terminal of the output unit 57 and connected at its CO terminal to the Ci terminal of the full adder 52 ₁₃.

The full adder 52 ₁₃ is connected at its s terminal to the S₄ terminal of the output unit 57 and connected at its CO terminal to the Ci terminal of the full adder 52 ₁₄.

The full adder 52 ₁₄ is connected at its s terminal to the S₅ terminal of the output unit 57 and connected at its CO terminal to the Ci terminal of the full adder 52 ₁₅.

The full adder 52 ₁₅ is connected at its s terminal to the S₆ terminal of the output unit 57 and connected at its CO terminal to the Ci terminal of the full adder 52 ₁₆.

The full adder 52 ₁₆ is connected at its in₁ terminal to the output terminal of the inverter 54 ₄, connected at its s terminal to the S₇ terminal of the output unit 57, and connected at its CO terminal to the S₈ terminal of the output unit 57 via the inverter 54 ₅.

Below, an explanation will be made of the operation of the processing apparatus 40 shown in FIG. 1.

FIG. 4 is a flow chart for explaining the processing method in the processing apparatus 40.

[Step S1]

Bit data A₀, B₀, A₁, B₁, A₂, B₂, A₃, and B₃ are input to the A₀, B₀, A₁, B₁, A₂, B₂, A₃, and B₃ terminals of the input unit 55. Further, the bit data C₀, C_(1, C) ₂, and C₃ are input to the C₀, C₁, C₂, and C₃ terminals of the input unit 56.

Then the selections of the bit data A₀ to A₃ and B₀ to B₃ at the multiplexers 50 ₀ to 50 ₁₅ shown below are simultaneously carried out, and the selected bit data are output to corresponding half adders and full adders.

Specifically, at the multiplexer 50 ₀, when the bit data C₀ has the logical value “1”, the bit data A₀ is output from the o terminal to the in₁ terminal of the half adder 53 ₁, while when the bit data C₀ has the logical value “0 ”, the bit data B₀ is output from the o terminal to the in₁ terminal of the half adder 53 ₁.

At the multiplexer 50 ₁, when the bit data C₀ has the logical value “1”, the bit data A₁ is output from the o terminal to the in₂ terminal of the full adder 52 ₁, while when the bit data C₀ has the logical value “0”, the bit data B₁ is output from the o terminal to the in₂ terminal of the full adder 52 ₁.

At the multiplexer 50 ₃, when the bit data C₀ has the logical value “1”, the bit data A₂ is output from the o terminal to the in₁ terminal of the half adder 53 ₂, while when the bit data C₀ has the logical value “0”, the bit data B₂ is output from the o terminal to the in₁ terminal of the half adder 53 ₂.

At the multiplexer 50 ₆, when the bit data C₀ has the logical value “1”, the bit data A₃ is output from the o terminal to the Ci terminal of the full adder 52 ₃, while when the bit data C₀ has the logical value “0”, the bit data B₃ is output from the o terminal to the Ci terminal of the full adder 52 ₃.

At the multiplexer 50 ₂, when the bit data C₁ has the logical value “1”, the bit data A₀ is output from the o terminal to the in₁ terminal of the full adder 52 ₁, while when the bit data C₁ has the logical value “0”, the bit data B₀ is output from the o terminal to the in₁ terminal of the full adder 52 ₁.

At the multiplexer 50 ₄, when the bit data C₁ has the logical value “1”, the bit data A₁ is output from the o terminal to the in₂ terminal of the full adder 52 ₂, while when the bit data C₁ has the logical value “0”, the bit data B₁ is output from the o terminal to the in₂ terminal of the full adder 52 ₂.

At the multiplexer 50 ₇, when the bit data C₁ has the logical value “1”, the bit data A₂ is output from the o terminal to the in₂ terminal of the full adder 52 ₃, while when the bit data C₁ has the logical value “0”, the bit data B₂ is output from the o terminal to the in₂ terminal of the full adder 52 ₃.

At the multiplexer 50 ₁₀, when the bit data C₁ has the logical value “1”, the bit data A₃ is output from the o terminal to the Ci terminal of the full adder 52 ₅, while when the bit data C₁ has the logical value “0”, the bit data B₃ is output from the o terminal to the Ci terminal of the full adder 52 ₅.

At the multiplexer 50 ₅, when the bit data C₂ has the logical value “1”, the bit data A₀ is output from the o terminal to the in₁ terminal of the full adder 52 ₂, while when the bit data C₂ has the logical value “0”, the bit data B₀ is output from the o terminal to the in₁ terminal of the full adder 52 ₂.

At the multiplexer 50 ₈, when the bit data C₂ has the logical value “1”, the bit data A₁ is output from the o terminal to the in₂ terminal of the half adder 53 ₃, while when the bit data C₂ has the logical value “0”, the bit data B₁ is output from the o terminal to the in₂ terminal of the half adder 53 ₃.

At the multiplexer 50 ₁₁, when the bit data C₂ has the logical value “1”, the bit data A₂ is output from the o terminal to the in₂ terminal of the full adder 52 ₅, while when the bit data C₂ has the logical value “0”, the bit data B₂ is output from the o terminal to the in₂ terminal of the full adder 52 ₂.

At the multiplexer 50 ₁₃, when the bit data C₂ has the logical value “1”, the bit data A₃ is output from the o terminal to the in₂ terminal of the full adder 52 ₈, while when the bit data C₂ has the logical value “0”, the bit data B₃ is output from the o terminal to the in₂ terminal of the full adder 52 ₈.

At the multiplexer 50 ₉, when the bit data C₃ has the logical value “1”, the bit data A₀ is output from the o terminal to the in₂ terminal of the half adder 53 ₃, while when the bit data C₃ has the logical value “0”, the bit data B₀ is output from the o terminal to the in₂ terminal of the half adder 53 ₃.

At the multiplexer 50 ₁₂, when the bit data C₃ has the logical value “1”, the bit data A₁ is output from the o terminal to the in₁ terminal of the full adder 52 ₅, while when the bit data C₃ has the logical value “0”, the bit data B₁ is output from the o terminal to the in₁ terminal of the full adder 52 ₅.

At the multiplexer 50 ₁₄, when the bit data C₃ has the logical value “1”, the bit data A₂ is output from the o terminal to the in₁ terminal of the full adder 52 ₈, while when the bit data C₃ has the logical value “0”, the bit data B₂ is output from the o terminal to the in₁ terminal of the full adder 52 ₈.

At the multiplexer 50 ₁₅, when the bit data C₃ has the logical value “1”, the bit data A₃ is output from the o terminal to the in₁ terminal of the full adder 52 ₁ while when the bit data C₃ has the logical value “0”, the bit data B₃ is output from the o terminal to the in₁ terminal of the full adder 52 ₁₀.

Further, the bit data B₀ from the B₀ terminal of the input unit 55 is output to the in₂ terminal of the half adder 53 ₁.

The bit data B₁ from the B₁ terminal of the input unit 55 is output to the Ci terminal of the full adder 52 ₁.

The bit data B₂ from the B₂ terminal of the input unit 55 is output to the in₂ terminal of the half adder 53 ₂.

The bit data B₃ from the B₃ terminal of the input unit 55 is output to the in₂ terminal of the full adder 52 ₄.

Further, the bit data B₀ from the B₀ terminal of the input unit 55 is inverted at the inverter circuit 54 ₁, and then output to the in₂ terminal of the full adder 52 ₆.

The bit data B₁ from the B₁ terminal of the input unit 55 is inverted at the inverter circuit 54 ₂, and then output to the Ci terminal of the full adder 52 ₈.

The bit data B₂ from the B₂ terminal of the input unit 55 is inverted at the inverter circuit 54 ₃, and then output to the in₂ terminal of the full adder 52 ₁₀.

The bit data B₃ from the B₃ terminal of the input unit 55 is inverted at the inverter circuit 54 ₄, and then output to the in₁ terminal of the full adder 52 ₁₆ of the final stage adder circuit 42

[Step S2]

At the half adder 53 ₁, the addition of the bit data B₀ and the bit data from the multiplexer 50 ₀ is carried out, the sum data of the related addition results is output from the s terminal to the S₀ terminal, and the carry data of the related addition result is output from the Co terminal to the in₂ terminal of the half adder 53 ₄ of the final stage adder circuit 42.

In the full adder 52 ₁, the addition of the bit data B₁, the bit data from the multiplexer 50 ₁ and the bit data from the multiplexer 50 ₂ is carried out, the sum data of the related addition results is output from the s terminal to the in₁ terminal of the half adder 53 ₅ of the final stage adder circuit 42, and the carry data of the related addition result is output from the Co terminal to the in₂ terminal of the full adder 52 ₁₁ of the final stage adder circuit 42.

At the half adder 53 ₂, the addition of the bit data B₂ and the bit data from the multiplexer 50 ₃ is carried out, the sum data of the related addition results is output from the s terminal to the Ci terminal of the full adder 52 ₂, and the carry data of the related addition result is output from the Co terminal to the Ci terminal of the full adder 52 ₄.

At the half adder 53 ₃, the addition of the bit data from the multiplexer 50 ₈ and the bit data from the multiplexer 50 ₉ is carried out, the sum data of the related addition results is output from the s terminal to the in₁ terminal of the full adder 52 ₃, and the carry data of the related addition result is output from the Co terminal to the in₂ terminal of the full adder 52 ₇.

At the full adder 52 ₅, the addition of the bit data from the multiplexer 50 ₁₀, the bit data from the multiplexer 50 ₁₁, and the bit data from the multiplexer 50 ₁₂ is carried out, the sum data of the related addition results is output from the s terminal to the in₁ terminal of the full adder 52 ₆, and the carry data of the related addition result is output from the Co terminal to the in₂ terminal of the full adder 52 ₉.

At the full adder 52 ₈, the bit data B₁ ⁻ from the inverter circuit 54 ₂, the bit data from the multiplexer 50 ₁₃, and the bit data from the multiplexer 50 ₁₄ are added, the sum data of the related addition results is output from the s terminal to the in₁ terminal of the full adder 52 ₉, and the carry data of the related addition result is output from the Co terminal to the Ci terminal of the full adder 52 ₁₀.

Further, at the full adder 52 ₂, the sum data from the half adder 53 ₂, the bit data from the multiplexer 50 ₄, and the bit data from the multiplexer 50 ₅ are added, the sum data of the related addition results is output from the s terminal to the in₁ terminal of the full adder 52 ₁₁ of the final stage adder circuit 42, and the carry data of the related addition result is output from the Co terminal to the in₂ terminal of the full adder 52 ₁₂ of the final stage adder circuit 42.

At the full adder 52 ₃, the bit data from the multiplexer 50 ₆, the bit data from the multiplexer 50 ₇, and the sum data from the half adder 53 ₃ are added, the sum data of the related addition results is output from the s terminal to the in₁ terminal of the full adder 52 ₄, and the carry data of the related addition result is output from the Co terminal to the Ci terminal of the full adder 52 ₇.

At the full adder 52 ₆, the addition of the logical value “1” input to the Ci terminal, the bit data B₁ ⁻ from the inverter 54 ₁, and the sum data from the s terminal of the full adder 52 ₅ is carried out, the sum data of the related addition results is output from the s terminal to the in₁ terminal of the full adder 52 ₇, and the carry data of the related addition result is output from the Co terminal to the Ci terminal of the full adder 52 ₉.

At the full adder 52 ₁₀, the carry data from the full adder 52 ₈, the bit data B₂ ⁻ from the inverter circuit 54 ₃, and the bit data from the multiplexer 50 ₁₅ are added, the sum data of the related addition results is output from the s terminal to the in₁ terminal of the full adder 52 ₁₅ of the final stage adder circuit 42, and the carry data of the related addition result is output from the Co terminal to the in₂ terminal of the full adder 52 ₁₆.

Further, at the full adder 52 ₄, the addition of the carry data from the half adder 53 ₂, the bit data B₃, and the sum data from the full adder 53 ₃ is carried out, the sum data of the related addition results is output from the s terminal to the in₁ terminal of the full adder 52 ₁₂ of the final stage adder circuit 42, and the carry data of the related addition result is output from the Co terminal to the in₂ terminal of the full adder 52 ₁₃.

At the full adder 52 ₇, the carry data from the full adder 52 ₃, the carry data from the half adder 53 ₃, and the sum data from the full adder 52 ₆ are added, the sum data of the related addition results is output from the s terminal to the in₁ terminal of the full adder 52 ₁₃ of the final stage adder circuit 42, and the carry data of the related addition result is output from the Co terminal to the in₂ terminal of the full adder 52 ₁₄ of the final stage adder circuit 42.

At the full adder 52 ₉, the carry data from the full adder 52 ₆, the carry data from the full adder 52 ₅, and the sum data from the full adder 52 ₈ are added, the sum data of the related addition results is output from the s terminal to the in₁ terminal of the full adder 52 ₁₄ of the final stage adder circuit 42, and the carry data of the related addition result is output from the Co terminal to the in₂ terminal of the full adder 52 ₁₅ of the final stage adder circuit 42.

[Step S3]

At the final stage adder circuit 42, the following processing is carried out.

First, at the half adder 53 ₄, the addition of the carry data from the half adder 53 ₁ and the sum data from the full adder 52 ₁ is carried out, the sum data thereof is output from the S₁ terminal of the output unit 57 as the bit data S₁, and the carry data thereof is output to the Ci terminal of the full adder 52 ₁₁.

Next, at the full adder 52 ₁₁, the carry data from the half adder 53 ₄, the carry data from the full adder 52 ₁, and the sum data from the full adder 52 ₂ are added, the sum data thereof is output from the S₂ terminal of the output unit 57 as the bit data S₂, and the carry data thereof is output to the Ci terminal of the full adder 52 ₁₂.

Next, at the full adder 52 ₁₂, the carry data from the full adder 52 ₁₁, the carry data from the full adder 52 ₂, and the sum data from the full adder 52 ₄ are added, the sum data thereof is output from the S₃ terminal of the output unit 57 as the bit data S₃, and the carry data thereof is output to the Ci terminal of the full adder 52 ₁₃.

Next, at the full adder 52 ₁₃, the carry data from the full adder 52 ₁₂, the carry data from the full adder 52 ₄, and the sum data from the full adder 52 ₇ are added, the sum data thereof is output from the S₄ terminal of the output unit 57 as the bit data S₄, and the carry data thereof is output to the Ci terminal of the full adder 52 ₁₄.

Next, at the full adder 52 ₁₄, the carry data from the full adder 52 ₁₃, the carry data from the full adder 52 ₇, and the sum data from the full adder 52 ₉ are added, the sum data thereof is output from the S₅ terminal of the output unit 57 as the bit data S₅, and the carry data thereof is output to the Ci terminal of the full adder 52 ₁₅.

Next, at the full adder 52 ₁₅, the carry data from the full adder 52 ₁₄, the carry data from the full adder 52 ₉, and the sum data from the full adder 52 ₀ are added, the sum data thereof is output from the S₆ terminal of the output unit 57 as the bit data S₆, and the carry data thereof is output to the Ci terminal of the full adder 52 ₁₆.

Next, at the full adder 52 ₁₆, the carry data from the full adder 52 ₁₅, the carry data from the full adder 52 ₁₀, and the bit data B₃ ⁻ from the inverter 54 ₄ are added, the sum data thereof is output from the S₇ of the output unit 57 as the bit data S₇, and the carry data thereof is output via the inverter 54 ₅ from the S₈ terminal of the output unit 57 as the bit data S₈.

Here, the bit data S₈ indicates the sign. When the bit data S₈ has the logical value “1”, it indicates that the data S of the result of the operation “(A−B)×C” is negative, while when the bit data S₈ has the logical value “0”, it indicates that the data S is positive.

Note that, when the bit data S₈ has the logical value “1”, the bit data S₀ to S₇ indicate the complement value of 2 of the result of the operation “(A−B)×C”.

In the processing apparatus 40 shown in FIG. 1, for example, as shown in FIG. 5, where data A (A₀, A₁, A₂, A₃)=(0, 0, 0, 1), B (B₀, B₁, B₂, B₃)=(0, 0, 1, 0) and C (C₀, C₁, C₂, C₃)=(1, 1, 1, 1) are input, data S (S₀, S₁, S₂, S₃, S₄, S₅, S₆, S₇, S₈)=(0, 1, 0, 1, 1, 0, 1, 0, 0) is output.

As explained above, according, to the processing apparatus 40, as shown in FIG. 1, the operation “(A−B)×C” can be carried out by the multiplexers 50 ₀ to 50 ₁₅, full adders (FA) 52 ₁ to 52 ₁₆ half adder (HA) 53 ₁ to 53 ₄, inverter circuits 54 ₁ to 54 ₄, input units 55 and 56, and the output unit 57. It is not necessary to use the multiplier of 5 bits as in the processing apparatus 1 of the related art shown in FIG. 6, FIG. 7, and FIG. 10 mentioned above, thus the circuit size can be greatly reduced.

Further, according to the processing apparatus 40, the critical path of the operation becomes the multiplexer 50 ₀, half adders 53 ₁ and 53 ₄, full adders 52 ₁₁, 52 ₁₂, 52 ₁₃, 52 ₁₄, 52 ₁₅, and 52 ₁₆, and the inverter circuit 54 ₅, so the critical path can be shortened compared with the processing apparatus 1 of the related art mentioned above, and thus the operation time can be shortened.

The embodiment of the present invention is not limited to that mentioned above.

For example, in FIG. 1, a case where the operation “(A−B)×C” was carried out by using 4-bit data A, B, and C was exemplified, but the present invention can be applied also to a case where the operation “(A−B)×C” is carried out by using n-bit data A, B, and C for all integers n of 2 or more.

In this case, the operation is carried out based on the following equation (9). $\begin{matrix} {S = {\left( {\sum\limits_{j = 0}^{j = {n - 1}}{\sum\limits_{i = 0}^{i = {n - 1}}{2^{i + j} \cdot P_{ij}}}} \right) - {2^{n} \times B} + B}} & (9) \end{matrix}$

In the above equation (9), the operation of the first term is carried out by the addition for every bit containing the carry data from the lower significant bit so as to select the bit data A_(i) when the bit data C_(j) has the logical value “1” by using the multiplexer as the bit data selecting means of the present invention, select the bit data B_(i) when the bit data C_(j) has the logical value “0”, and add the selected data to the (i+j)th bit.

Further, in the above equation (9), the operation of “−2^(n)×B” is carried out by finding the complement of 2 of the data B by inverting the level of the data B, adding “1” to the LSB of this level-inverted data, and shifting the addition result by exactly n bits toward the MSB. The shift is realized by inputting for example bit data B₀ to B_(n−1) as the addition result to the adder for performing the addition corresponding to (n to 2n−1)th bits of the result.

Then, by adding the result of the first term of the above equation (9), the result of “−2^(n)×B”, and the data B, the operation of the above equation (9) is carried out.

Summarizing the effect of the invention, as explained above, according to the processing apparatus of the present invention and the method of same, the time of the operation “(A−B)×C” can be shortened.

Further, according to the processing apparatus of the present invention, the size of the device for performing the operation “(A−B)×C” can be reduced.

While the invention has been described by reference to specific embodiments chosen for purposes of illustration, it should be apparent that numerous modifications could be made thereto by those skilled in the art without departing from the basic concept and scope of the invention. 

What is claimed is:
 1. A processing apparatus for calculating “(A−B)×C” where the bit data A is constituted by the n-bit data of A_(i) (i=0, 1, . . . n−1), the bit data B is constituted by the n-bit data of B_(i) (i=0, 1, . . . n−1), and the bit data C is constituted by the n-bit data of C_(j) (j=0, 1, . . . n−1), said processing apparatus comprising: a bit data selecting means for receiving as input the bit data A_(i), B_(i), and C_(j), and outputting the bit data A_(i) when C_(j) equals to a first logical value or the bit data B_(i) when data C_(j) equals to a second logical value in response to data C_(j) with respect to all combinations of the natural numbers i and j; and, an adding means for adding the bit data output from the bit data selecting means to the (i+j)th bit for each bit of all combinations of i and j, the data obtained by shifting the data of the complement of 2 of the data B by exactly n number of bits toward the most significant bit, and the data B.
 2. A processing apparatus as set forth in claim 1, wherein said bit selecting means includes (n-rows)×(n-columns) number of bit selectors, and the bit selector of i-th row and j-th column inputs the bit data A_(i) and B_(i) and outputs the bit data A_(i) or B_(i) in response to the bit data C_(j).
 3. A processing apparatus as set forth in claim 1, further comprising an inverted value generating means for inverting the bit data B₀, B₁, . . . , B_(i), . . . , B_(n−2), and B_(n−1) to find the bit data B₀ ⁻, B₁ ⁻, . . . , B_(i) ⁻, . . . , B_(n−2) ⁻, and B_(n−1) ⁻; said adding means respectively adds the bit data B₁ ⁻, . . . . , B_(i) ⁻, . . . , B_(n−1) ⁻ found by the inverted value generating means to the (n+1)th, . . . , (n+i)th, . . . , (2n−1)th bits; and adds the bit data B₀ ⁻ and the logical value “1” to the n-th bit.
 4. A processing apparatus as set forth in claim 1, wherein said adding means adds the bit data B₀, B₁, . . . , B_(i), . . . , B_(n−2), and B_(n−1) of the data B to the 0th, 1st, . . . , i-th, . . . , (n−2)th, and (n−1)th bits.
 5. A processing apparatus as set forth in claim 1, wherein: the adding means outputs as the result of the addition (2n+1)bit data comprised of the bit data S₀, S₁, . . . , S^(2n−), and S_(2n) and the bit data S_(2n) shows the sign value.
 6. A processing apparatus as set forth in claim 1, wherein the bit data selecting means each has a first transmission gate which becomes conductive when the input bit data C_(i) is the first logical value and a second transmission gate which becomes conductive when the input bit data C_(i) is the second logical value.
 7. A processing method for calculating “(A−B)×C” where the bit data A is constituted by the n-bit data of A_(i) (i=0, 1, . . . n−1), the bit data B is constituted by the n-bit data of B_(i) (i=0, 1, . . . n−1), and the bit data C is constituted by the n-bit data of C_(j) (J=0, 1, . . . n−1), said processing method comprising the steps of: performing processing for receiving as input the bit data A_(i), B_(i), and C_(j), selecting the bit data A_(i) when data C_(j) equals to a first logical value or B_(i) when data C_(j) equals to a second logical value in response to the bit data C_(j) with respect to all combinations of the natural numbers i and j; and adding the selected bit data to the (i+j)th bit for each bit of all combinations of i and j, the data obtained by shifting the data of the complement of 2 of the data B by exactly n number of bits toward the most significant bit, and the data B.
 8. A processing method as set forth in claim 7, further comprising the steps of: inverting the bit data B₀, B₁, . . . , B_(i), . . . , B_(n−2), and B_(n−1) to find the bit data B₀ ⁻, B₁ ⁻, . . . , B₁ ⁻, . . . , B_(n−2) ³¹ , and B_(n−1) ⁻; adding the bit data B₁ ⁻, . . . B_(i) ⁻, . . . , B_(n−1) ⁻ to the (n+1)th, . . . , (n+i)th, . . . , (2n−1)th bits; and adding the bit data B₀ ⁻ and the logical value “1” to the n-th bit.
 9. A processing method as set forth in claim 7, further comprising the step adding the bit data B₀, B₁, . . . , B_(i), . . . , B_(n−2), and B_(n−1) of the data B to the 0th, 1st, . . . , i-th, . . . , (n−2)th, and (n−1)th bits.
 10. A processing method as set forth in claim 7, further comprising the step of: outputting as the result of the addition (2n+1)bit data comprised of the bit data S₀, S₁, . . . , S_(2n−1), and S_(2n) and the bit data S_(2n) indicating the sign value. 